* a variabledepth FIFO which can be adjusted to delay the output data up to 4 parallel data clock periods. Ancilliary data may be selectively extracted from the parallel data through the use of masking and control bits in the configuration and control registers and stored in the on-chip FIFO. Reverse
CLC031
National Semiconductor
416.44 KB
Smpte 292m/259m digital video deserializer / descrambler.
www.DataSheet4U.com CLC031 SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancilliary Data FIFOs PRELIMINARY August 2003 CL.
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