DM54LS502 Datasheet - National Semiconductor

DM54LS502 8-Bit Successive Approximation Register

The LS502 is an 8-bit register with the interstage logic necessary to perform serial-to-parallel conversion and provide an active LOW Conversion Complete (CC) signal coincident with storage of the eighth bit An active LOW Start (S) input performs synchronous initialization which forces Q7 LOW and al.

DM54LS502 Features

* Y Y Y Low power Schottky version of 2502 Storage and control for successive approximation A to D conversion Performs serial-to-parallel conversion Connection Diagram Dual-In-Line Package Logic Symbol TL F 10189

* 2 VCC e Pin 16 GND e Pin 8 TL F 10189

* 1 Order Number DM54LS502

DM54LS502 Datasheet (133.13 KB)