DM54LS502 Datasheet, Register, National Semiconductor

DM54LS502 Features

• Register Y Y Y Low power Schottky version of 2502 Storage and control for successive approximation A to D conversion Performs serial-to-parallel conversion Connection Diagram Dual-In-Line Pac

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DM54LS502

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National Semiconductor

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133.13kb

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📄 Datasheet

Description:

8-bit successive approximation register. The LS502 is an 8-bit register with the interstage logic necessary to perform serial-to-parallel conversion and provide an active LOW

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📁 Related Datasheet

DM54LS503 - 8-Bit Successive Approximation Register (National Semiconductor)
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DM54LS00 - Quad 2-Input NAND Gates (National Semiconductor)
54LS00 DM54LS00 DM74LS00 Quad 2-Input NAND Gates June 1989 54LS00 DM54LS00 DM74LS00 Quad 2-Input NAND Gates General Description This device contains.

DM54LS02 - Quad 2-Input NOR Gates (National Semiconductor)
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DM54LS03 - Quad 2-Input NAND Gates with Open-Collector Outputs (National Semiconductor)
54LS03 DM54LS03 DM74LS03 Quad 2-Input NAND Gates with Open-Collector Outputs June 1989 54LS03 DM54LS03 DM74LS03 Quad 2-Input NAND Gates with Open-Co.

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DM54LS08 - Quad 2-Input AND Gates (National Semiconductor)
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DM54LS10 - Triple 3-Input NAND Gates (National Semiconductor)
54LS10 DM54LS10 DM74LS10 Triple 3-Input NAND Gates June 1989 54LS10 DM54LS10 DM74LS10 Triple 3-Input NAND Gates General Description This device cont.

DM54LS109A - Dual Positive-Edge-Triggered J-K Flip-Flops with Preset/ Clear/ and Complementary Outputs (National Semiconductor)
54LS109 DM54LS109A DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset Clear and Complementary Outputs June 1989 54LS109 DM54LS109A D.

DM54LS11 - Triple 3-Input AND Gates (National Semiconductor)
54LS11 DM54LS11 DM74LS11 Triple 3-Input AND Gates June 1989 54LS11 DM54LS11 DM74LS11 Triple 3-Input AND Gates General Description This device contai.

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