DM54LS503 Datasheet, Register, National Semiconductor

DM54LS503 Features

• Register Y Performs serial-to-parallel conversion Y Expansion control for longer words Y Storage and control for

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DM54LS503

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National Semiconductor

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📄 Datasheet

Description:

8-bit successive approximation register. The ’LS503 register is basically the same as the ’LS502 except that it has an active LOW Enable (E) input that is used in cascading t

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DM54LS503

National Semiconductor

📁 Related Datasheet

DM54LS502 - 8-Bit Successive Approximation Register (National Semiconductor)
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DM54LS00 - Quad 2-Input NAND Gates (National Semiconductor)
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DM54LS02 - Quad 2-Input NOR Gates (National Semiconductor)
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DM54LS03 - Quad 2-Input NAND Gates with Open-Collector Outputs (National Semiconductor)
54LS03 DM54LS03 DM74LS03 Quad 2-Input NAND Gates with Open-Collector Outputs June 1989 54LS03 DM54LS03 DM74LS03 Quad 2-Input NAND Gates with Open-Co.

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DM54LS08 - Quad 2-Input AND Gates (National Semiconductor)
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DM54LS10 - Triple 3-Input NAND Gates (National Semiconductor)
54LS10 DM54LS10 DM74LS10 Triple 3-Input NAND Gates June 1989 54LS10 DM54LS10 DM74LS10 Triple 3-Input NAND Gates General Description This device cont.

DM54LS109A - Dual Positive-Edge-Triggered J-K Flip-Flops with Preset/ Clear/ and Complementary Outputs (National Semiconductor)
54LS109 DM54LS109A DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset Clear and Complementary Outputs June 1989 54LS109 DM54LS109A D.

DM54LS11 - Triple 3-Input AND Gates (National Semiconductor)
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