DM74LS379 - Quad Parallel Register
DM74LS379 Features
* the common Enable rather than common Master Reset Features Y Y Y Y Edge-triggered D-type inputs Buffered positive edge-triggered clock Buffered common enable input True and complement outputs Connection Diagram Dual-In-Line Package Logic Symbol TL F 10186
* 2 TL F 10186
* 1 VC
