MC100EP195 Datasheet - ON Semiconductor

MC100EP195 3.3V ECL Programmable Delay Chip

Pin Name I/O Default State Description 23, 25, 26, 27, D[0:9] LVCMOS, LVTTL, Low Single *Ended Parallel Data Inputs [0:9]. Internal 75 kW to VEE. 29, 30, 31, 32, ECL Input (Note 1) 1, 2 3 4 5 6 7 8 9, 24, 28 D[10] IN IN LVCMOS, LVTTL, ECL Input ECL Input ECL Input VBB

3.3 V ECL Programmable Delay Chip MC100EP195 The MC100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and www.onsemi.com multiplexers as shown in the logic diagram, Figure 3. The delay increment of the EP195 has a digitally selectable resolution of about 10 ps and a net range of up to 10.2 ns. The requ.

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