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MC100EP196A 3.3 V ECL Programmable Delay Chip

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Description

MC100EP196A 3.3 V ECL Programmable Delay Chip With FTUNE The MC100EP196A is a Programmable Delay Chip (PDC) designed primarily for clock deskewing .
Pin Name I/O Default State Description 23, 25, 26, 27, D[0:9] LVCMOS, LVTTL, Low Single. Ended Parallel Data Inputs [0:9].

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Features

* Parameter Condition 1 Condition 2 Rating Unit VCC Positive Mode Power Supply VEE Negative Mode Power Supply VI Positive Mode Input Voltage Negative Mode Input Voltage Iout Output Current VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI ≤ VCC VI ≥ VEE 6V
* 6 V 6V
* 6

MC100EP196A Distributors

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3.3 ECL Programmable Delay Chip ON Semiconductor
ON Semiconductor MC100EP196A-like datasheet