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MC100EP196B - 3.3 V ECL Programmable Delay Chip

Datasheet Summary

Description

primarily for clock deskewing and timing adjustment.

delay of a differential NECL/PECL input transition.

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Datasheet preview – MC100EP196B

Datasheet Details

Part number MC100EP196B
Manufacturer ON Semiconductor
File Size 161.50 KB
Description 3.3 V ECL Programmable Delay Chip
Datasheet download datasheet MC100EP196B Datasheet
Additional preview pages of the MC100EP196B datasheet.

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Full PDF Text Transcription

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MC100EP196B 3.3 V ECL Programmable Delay Chip With FTUNE Descriptions The MC100EP196B is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar architecture to the EP195 with the added feature of further tunability in delay using the FTUNE pin. The FTUNE input takes an analog voltage from VCC to VEE to fine tune the output delay from 0 to 60 ps. The delay section consists of a programmable matrix of gates and multiplexers as shown in the logic diagram, Figure 3. The delay increment of the EP196B has a digitally selectable resolution of about 10 ps and a net range of up to 10.4 ns.
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