Datasheet4U Logo Datasheet4U.com

MC100EP195 - 3.3V ECL Programmable Delay Chip

Datasheet Summary

Description

Pin Name I/O Default State Description 23, 25, 26, 27, D[0:9] LVCMOS, LVTTL, Low Single

Ended Parallel Data Inputs [0:9].

Internal 75 kW to VEE.

📥 Download Datasheet

Datasheet preview – MC100EP195

Datasheet Details

Part number MC100EP195
Manufacturer ON Semiconductor
File Size 303.17 KB
Description 3.3V ECL Programmable Delay Chip
Datasheet download datasheet MC100EP195 Datasheet
Additional preview pages of the MC100EP195 datasheet.

📁 Similar Datasheet

  • MC100EP111 - LOW-VOLTAGE 1:10 DIFFERENTIAL ECL/PECL CLOCK DRIVER (Motorola)
  • MC100EP221 - LOW-VOLTAGE 1:20 DIFFERENTIAL ECL/PECL CLOCK DRIVER (Motorola)
  • MC100EP223 - Low Voltage 1:22 Differential PECL/HSTL Clock Driver (Motorola Semiconductor)
  • MC100E016 - 8-Bit Synchronous Binary Up Counter (Motorola)
  • MC100E101 - Quad 4-Input OR/NOR Gate (Motorola)
  • MC100E104 - QUINT 2-INPUT AND/NAND GATE (Motorola)
  • MC100E107 - QUINT 2-INPUT XOR/XNOR GATE (Motorola)
  • MC100E111 - 1:9 DIFFERENTIAL CLOCK DRIVER (Motorola)
  • MC100E112 - QUAD DRIVER (Motorola)
  • MC100E116 - QUINT DIFFERENTIAL LINE RECEIVER (Motorola)
Other Datasheets by ON Semiconductor
  • MC100EP195B - 3.3V ECL Programmable Delay Chip
  • MC100EP196 - 3.3V ECL Programmable Delay Chip
  • MC100EP196A - 3.3 V ECL Programmable Delay Chip
  • MC100EP196B - 3.3 V ECL Programmable Delay Chip
  • MC100EP101 - 3.3V / 5V ECL Quad 4-Input OR/NOR
  • MC100EP105 - 3.3V / 5VECL Quad 2-Input Differential AND/NAND
  • MC100EP11 - 3.3V / 5VECL 1:2 Differential Fanout Buffer
  • MC100EP116 - 3.3 V / 5 V Hex Differential Line Receiver/Driver

Full PDF Text Transcription

Click to expand full text
3.3 V ECL Programmable Delay Chip MC100EP195 The MC100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and www.onsemi.com multiplexers as shown in the logic diagram, Figure 3. The delay increment of the EP195 has a digitally selectable resolution of about 10 ps and a net range of up to 10.2 ns. The required delay is selected by the 10 data select inputs D[9:0] values and controlled by the LEN (pin 10). A LOW level on LEN allows a transparent LOAD mode of 1 32 real time delay values by D[9:0].
Published: |