MC100LVEL39 Datasheet - ON Semiconductor

Clock Generation Chip

MC100LVEL39 Features

* www.onsemi.com SOIC

* 20 WB DW SUFFIX CASE 751D MARKING DIAGRAM

* 20 100LVEL39 AWLYYWWG 1 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb-Free Package

* For additional marking information, refer to Application Note AND8002/D.

* 50 ps Maximum Output-to-Outpu

MC100LVEL39 General Description

The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or singl.

MC100LVEL39 Datasheet (141.03 KB)