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MC10E150 - 6-BIT D LATCH

Datasheet Summary

Description

The MC10E/100E150 contains six D-type latches with differential outputs.

When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent and input data transitions propagate through to the output.

A logic HIGH on either LEN1 or LEN2 (or both) latches the data.

Features

  • http://onsemi. com.
  • 800 ps Max. Propagation Delay.
  • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V.
  • with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE =.
  • 4.2 V to.
  • 5.7 V Internal Input 50 kW Pulldown Resistors ESD Protection: Human Body Model; > 2 kV, Machine Model; > 200 V Charged Device Model; > 2 kV Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test Moisture Sensitivity Level: Pb = 1 Pb.

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Datasheet Details

Part number MC10E150
Manufacturer ON Semiconductor
File Size 105.41 KB
Description 6-BIT D LATCH
Datasheet download datasheet MC10E150 Datasheet
Additional preview pages of the MC10E150 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com MC10E150, MC100E150 5V ECL 6-Bit D Latch Description The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the data. The Master Reset (MR) overrides all other controls to set the Q outputs low. The 100 Series contains temperature compensation. Features http://onsemi.com • 800 ps Max. Propagation Delay • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V • • • • • with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.
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