NB3RL02 Datasheet - ON Semiconductor

NB3RL02 Low Phase-Noise Two-Channel Clock Fanout Buffer

Ball No. Name A1 VBATT A2 CLK_OUT1 B1 VLDO B2 CLK_REQ1 C1 MCLK_IN C2 CLK_REQ2 D1 GND D2 CLK_OUT2 I/O Description I Input to internal LDO O Clock output 1 O 1.8 V supply for NB3RL02 and external TCXO I Clock request from peripheral 1 I Master clock input I Clock reques.

NB3RL02 Low Phase-Noise Two-Channel Clock Fanout Buffer The NB3RL02 is a low skew, low jitter 1:2 clock fan out buffer, ideal for use in portable end equipment, such as mobile phones. With integrated LDO and output control circuitry. The MCLK_IN pin has an AC coupling capacitor and will directly accept a square or sine wave clock input, such as a temperature compensated crystal oscillator (TCXO). The minimum acceptable input amplitude of the sine wave is 300 mV peak <.

NB3RL02 Features

* Low Additive Noise:

* 149 dBc/Hz at 10 kHz Offset Phase Noise

* 0.37 ps (rms) Output Jitter

* Limited Output Slew Rate for EMI Reduction (1 ns to 5 ns/Rise/Fall Time for 10

* 50 pF Loads)

* Regulated 1.8 V Output Supply Available for External

NB3RL02 Datasheet (277.47 KB)