* r>
* is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs. AC WAVEFORMS tW(H) tW(L) CP 1.3 V tPHL 1.3 V tPLH Other conditions: PE = MR (SR) = H CEP = CET = H Q 1.3 V 1
SN74LS161A Datasheet (195.43 KB)
SN74LS161A
195.43 KB
Bcd decade counters / 4-bit binary counters.
SN74LS161A, SN74LS163A BCD Decade Counters/ 4 Bit Binary Counters The LS161A/163A are high-speed 4-bit synchronous counters. They are edge-tr.
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