PI6C2502 Datasheet | Pericom Semiconductor

Features - High-Performance Phase-Locked-Loop Clock Distribution for Networking, - Synchronous DRAM modules for server/workstation/ PC applications - Allows Clock Input to have Spread Spectrum modulation for EMI reduction - Zero Input-to-Output delay - Low jitter: Cycle-to-Cycle jitter ±100ps max. - On-chip series damping resistor at clock output drivers for low noise and EMI reduction - Operates at 3.3V VCC - Wide range of Clock Frequencies up to 80 MHz - Package: Plastic 8-pin SOIC Package (W) Product Description The PI6C2502 features a low-skew, low-jitter, phase-locked loop (PLL) clock driver. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. Application If a system designer needs more than 16 outputs with the features just described, using two or more zero-delay buffers such as PI6C2509Q, and PI6C2510Q, is likely to be impractical. The device-to-device skew introduced can significantly reduce the performance. Peri remends the use of a zero-delay buffer and an eighteen output non-zero-delay buffer. As shown in Figure 1, this bination produces a zero-delay buffer with all the signal characteristics of the original zero-delay buffer, but with as many outputs as the non-zero-delay buffer part. For example, when bined with an eighteen output non-zero delay buffer, a system designer can create a seventeen-output zero-delay buffer. Logic Block Diagram Product Pin Configuration CLK_IN FB_IN AVCC CLK_OUT FB_OUT AGND FB_OUT 1 2 3 4 CLK_OUT VCC 8-Pin W 8 7 6 5 CLK_IN AVCC GND FB_IN Feedback Zero Delay Buffer PI6C2502 Reference Clock Signal CLK_OUT 18 Output Non-Zero Delay Buffer Figure 1. This bination Provides Zero-Delay Between the Reference Clocks Signal and 17 Outputs PS8382B 03/20/02 PI6C2502 Phase-Locked Loop Clock Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901...