PI6C5930 Low Skew CMOS PLL Clock Driver

Pericom Semiconductor

Description

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The PI6C5930 clock driver uses a PLL (phase-locked loop) to reduce time skew between a reference clock input (SYNC) and the outputs.

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Datasheet Specifications

Part number: PI6C5930
Manufacturer: Pericom Semiconductor
File Size: 216.77 KB
Datasheet: PI6C5930_PericomSemiconductor.pdf
Description: Low Skew CMOS PLL Clock Driver

Features

* Wide frequency range: 100 MHz max.
* Five Q and one Q/2 outputs
* Output skew < 250ps (rising edges)
* Internal RC loop filter network
* Low noise TTL-compatible outputs
* Balanced drive outputs: +24mA
* Outputs Hi-Z and registers reset when

PI6C5930 Distributors

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PI6C5930 Low Skew CMOS PLL Clock Driver Pericom Semiconductor

Pericom Semiconductor PI6C5930-like datasheet