PLL130-09 Datasheet (PhaseLink Corporation) - High Speed Translator Buffer to LVDS

PLL130-09, High Speed Translator Buffer to LVDS

The PLL130-09 is a low cost, high performance, high speed, buffer that reproduces any input frequency from DC to 1.0GHz.

It provides a pair of differential LVDS output.

Any input signal with at least 100mV swing can be used as reference signal.

This chip is ideal for conversion from sine wave, TTL,

PLL130-09 Features

* Differential LVDS output Single AC coupled input (min. 100mV swing). Input range from DC to 1.0 GHz. 2.5V to 3.3V operation. Available in 8-Pin SOIC or 3x3mm QFN. PIN CONFIGURATION (TOP VIEW) GND REF_IN 1 2 3 4 VDD 8 7 6 5 GND VDD GND LVDS_BAR VD