Datasheet4U Logo Datasheet4U.com

PLL130-09

High Speed Translator Buffer to LVDS

PLL130-09 Features

* Differential LVDS output Single AC coupled input (min. 100mV swing). Input range from DC to 1.0 GHz. 2.5V to 3.3V operation. Available in 8-Pin SOIC or 3x3mm QFN. PIN CONFIGURATION (TOP VIEW) GND REF_IN 1 2 3 4 VDD 8 7 6 5 GND VDD GND LVDS_BAR VD

PLL130-09 General Description

The PLL130-09 is a low cost, high performance, high speed, buffer that reproduces any input frequency from DC to 1.0GHz. It provides a pair of differential LVDS output. Any input signal with at least 100mV swing can be used as reference signal. This chip is ideal for conversion from sine wave, TTL, .

PLL130-09 Datasheet (269.84 KB)

Preview of PLL130-09 PDF

Datasheet Details

Part number:

PLL130-09

Manufacturer:

PhaseLink Corporation

File Size:

269.84 KB

Description:

High speed translator buffer to lvds.

📁 Related Datasheet

PLL130-05 High Speed Translator Buffer to PECL (PhaseLink Corporation)

PLL130-07 High Speed Translator Buffer to CMOS (PhaseLink Corporation)

PLL130-08 High Speed Translator Buffer to PECL (PhaseLink Corporation)

PLL130-68 High Speed Translator Buffers (PhaseLink Corporation)

PLL130-69 High Speed Translator Buffers (PhaseLink Corporation)

PLL1000A PHASE LOCKED LOOP (Z-Communications)

PLL102-03 Low Skew Output Buffer (PhaseLink Corporation)

PLL102-04 Low Skew Output Buffer (PhaseLink Corporation)

PLL102-05 Low Skew Output Buffer (PhaseLink Corporation)

PLL102-10 Low Skew Output Buffer (PhaseLink Corporation)

TAGS

PLL130-09 High Speed Translator Buffer LVDS PhaseLink Corporation

Image Gallery

PLL130-09 Datasheet Preview Page 2 PLL130-09 Datasheet Preview Page 3

PLL130-09 Distributor