PLL102-03 Datasheet - PhaseLink Corporation

PLL102-03 Low Skew Output Buffer

The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input of the PLL. S.

PLL102-03 Features

* Frequency range 75 ~ 180MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation).

* Zero input - output delay.

* Less than 700 ps device - device skew.

* Less than 250 ps skew between outputs

PLL102-03_PhaseLinkCorporation.pdf