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PLL102-108 Programmable DDR Zero Delay Clock Driver

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Description

PLL102-108 Programmable DDR Zero Delay Clock Driver .
The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock o.

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Datasheet Specifications

Part number
PLL102-108
Manufacturer
PhaseLink Corporation
File Size
198.33 KB
Datasheet
PLL102-108_PhaseLinkCorporation.pdf
Description
Programmable DDR Zero Delay Clock Driver

PLL102-108 Distributors

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PhaseLink Corporation PLL102-108-like datasheet