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PLL102-108 Datasheet - PhaseLink Corporation

PLL102-108_PhaseLinkCorporation.pdf

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Datasheet Details

Part number:

PLL102-108

Manufacturer:

PhaseLink Corporation

File Size:

198.33 KB

Description:

Programmable ddr zero delay clock driver.

PLL102-108, Programmable DDR Zero Delay Clock Driver

The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output.

Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK_INT.

The PLL can be bypassed for test purposes by strapping

PLL102-108 Features

* PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz.

* Distributes one clock Input to one bank of ten differential outputs.

* Track spread spectrum clocking for EMI reduction.

* Programmable delay between CLK_INT and CLK[T/C] from

* 0.8

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