PLL102-108 - Programmable DDR Zero Delay Clock Driver

PhaseLink Corporation

PLL102-108 Datasheet Preview — Preview of PLL102-108 PDF

Datasheet Details

Part number	PLL102-108
Manufacturer	PhaseLink Corporation
File Size	198.33 KB
Description	Programmable DDR Zero Delay Clock Driver
Datasheet	PLL102-108_PhaseLinkCorporation.pdf

PLL102-108 Product details

Description

The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output.

Features

PLL clock distribution optimized for Double Data Rate SDRAM.

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Other Datasheets by PhaseLink Corporation

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Published: Oct 28, 2008 |