PLL102-15 - Low Skew Output Buffer

PhaseLink Corporation

PLL102-15 Datasheet Preview — Preview of PLL102-15 PDF

Datasheet Details

Part number	PLL102-15
Manufacturer	PhaseLink Corporation
File Size	141.06 KB
Description	Low Skew Output Buffer
Datasheet	PLL102-15_PhaseLinkCorporation.pdf

PLL102-15 Product details

Description

The PLL102 -15 is a high performance, low skew, low jitter zero delay buffer designed to di stribute high speed clocks and is available in 8 -pin SOIC or TSSOP package.

Features

Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spec trum modulation on reference clock to pass to the outputs (up to 33kHz SST modulation).
Zero input - output delay.
Less than 700 ps device - device skew.
Less than 250 ps skew between outputs. www. DataSheet4U. com.
Less than 200 ps cycle - cycle jitter.
Output Enable function tri -state outputs.
3.3V operation.
Available in 8 -Pin 150mil SOIC.

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Other Datasheets by PhaseLink Corporation

PLL102-10 - Low Skew Output Buffer
PLL102-108 - Programmable DDR Zero Delay Clock Driver
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PLL102-03 - Low Skew Output Buffer
PLL102-04 - Low Skew Output Buffer
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Published: Oct 28, 2008 |