PLL102-15 Datasheet - PhaseLink Corporation

PLL102-15 Low Skew Output Buffer

The PLL102 -15 is a high performance, low skew, low jitter zero delay buffer designed to di stribute high speed clocks and is available in 8 -pin SOIC or TSSOP package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feedback to the input of t.

PLL102-15 Features

* Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spec trum modulation on reference clock to pass to the outputs (up to 33kHz SST modulation).

* Zero input - output delay.

* Less than 700 ps device - device skew.

* Less than 250 ps skew between outputs.

PLL102-15_PhaseLinkCorporation.pdf