Datasheet4U Logo Datasheet4U.com

PLL102-15

Low Skew Output Buffer

PLL102-15 Features

* Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spec trum modulation on reference clock to pass to the outputs (up to 33kHz SST modulation).

* Zero input - output delay.

* Less than 700 ps device - device skew.

* Less than 250 ps skew between outputs.

PLL102-15 General Description

The PLL102 -15 is a high performance, low skew, low jitter zero delay buffer designed to di stribute high speed clocks and is available in 8 -pin SOIC or TSSOP package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feedback to the input of t.

PLL102-15 Datasheet (141.06 KB)

Preview of PLL102-15 PDF

Datasheet Details

Part number:

PLL102-15

Manufacturer:

PhaseLink Corporation

File Size:

141.06 KB

Description:

Low skew output buffer.

📁 Related Datasheet

PLL102-10 Low Skew Output Buffer (PhaseLink Corporation)

PLL102-108 Programmable DDR Zero Delay Clock Driver (PhaseLink Corporation)

PLL102-109 Programmable DDR Zero Delay Clock Driver (PhaseLink Corporation)

PLL102-03 Low Skew Output Buffer (PhaseLink Corporation)

PLL102-04 Low Skew Output Buffer (PhaseLink Corporation)

PLL102-05 Low Skew Output Buffer (PhaseLink Corporation)

PLL1000A PHASE LOCKED LOOP (Z-Communications)

PLL103-01 Low Skew Buffer (PhaseLink Corporation)

PLL103-02 DDR SDRAM Buffer (PhaseLink Corporation)

PLL103-03 DDR SDRAM Buffer (PhaseLink Corporation)

TAGS

PLL102-15 Low Skew Output Buffer PhaseLink Corporation

Image Gallery

PLL102-15 Datasheet Preview Page 2 PLL102-15 Datasheet Preview Page 3

PLL102-15 Distributor