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PLL102-109

Programmable DDR Zero Delay Clock Driver

PLL102-109 Features

* PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz.

* Distributes one clock Input to one bank of six differential outputs.

* Track spread spectrum clocking for EMI reduction.

* Programmable delay between CLK_INT and CLK[T/C] from

* 0.8

PLL102-109 General Description

The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purposes by strapping.

PLL102-109 Datasheet (199.76 KB)

Preview of PLL102-109 PDF

Datasheet Details

Part number:

PLL102-109

Manufacturer:

PhaseLink Corporation

File Size:

199.76 KB

Description:

Programmable ddr zero delay clock driver.

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TAGS

PLL102-109 Programmable DDR Zero Delay Clock Driver PhaseLink Corporation

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