Part number:
PLL102-109
Manufacturer:
PhaseLink Corporation
File Size:
199.76 KB
Description:
Programmable ddr zero delay clock driver.
PLL102-109_PhaseLinkCorporation.pdf
Datasheet Details
Part number:
PLL102-109
Manufacturer:
PhaseLink Corporation
File Size:
199.76 KB
Description:
Programmable ddr zero delay clock driver.
PLL102-109, Programmable DDR Zero Delay Clock Driver
The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output.
Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK_INT.
The PLL can be bypassed for test purposes by strapping
PLL102-109 Features
* PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz.
* Distributes one clock Input to one bank of six differential outputs.
* Track spread spectrum clocking for EMI reduction.
* Programmable delay between CLK_INT and CLK[T/C] from
* 0.8
📁 Related Datasheet
📌 All Tags