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PLL102-109 Programmable DDR Zero Delay Clock Driver

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Description

Preliminary PLL102-109 Programmable DDR Zero Delay Clock Driver .
The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock o.

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Datasheet Specifications

Part number
PLL102-109
Manufacturer
PhaseLink Corporation
File Size
199.76 KB
Datasheet
PLL102-109_PhaseLinkCorporation.pdf
Description
Programmable DDR Zero Delay Clock Driver

PLL102-109 Distributors

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PhaseLink Corporation PLL102-109-like datasheet