PLL102-10 Datasheet - PhaseLink Corporation

PLL102-10 Low Skew Output Buffer

The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input of the PL.

PLL102-10 Features

* Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to outputs.

* Zero input - output delay.

* Less than 700 ps device - device skew.

* Less than 250 ps skew between outputs. www.DataSheet4U.com

* Le

PLL102-10_PhaseLinkCorporation.pdf