PLL102-10 Low Skew Output Buffer

PhaseLink Corporation

Description

PLL102-10 Low Skew Output Buffer .
The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or.

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Datasheet Specifications

Part number: PLL102-10
Manufacturer: PhaseLink Corporation
File Size: 213.29 KB
Datasheet: PLL102-10_PhaseLinkCorporation.pdf
Description: Low Skew Output Buffer

Features

* Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to outputs.
* Zero input - output delay.
* Less than 700 ps device - device skew.
* Less than 250 ps skew between outputs. www. DataSheet4U. com
* Le

Applications

* requiring zero output-output skew, all the outputs must be equally loaded. www. DataSheet4U. com If the CLK(1-2) outputs are less loaded than CLKOUT, CLK(1-2) outputs will lead it; if the CLK(1-2) is more loaded than CLKOUT, CLK(1-2) will lag the CLKOUT. Since the CLKOUT and the CLK(1-2) outputs are

PLL102-10 Distributors

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PLL102-10 Low Skew Output Buffer PhaseLink Corporation

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