PLL1000A Datasheet, Loop, Z-Communications

PLL1000A Features

• Loop
• Frequency Range: 988 - 1028 MHz
• Step Size: 1000 KHz
• PLL - Style Package APPLICATIONS
• Basestations
• Mobile Radios
• Satellite Com

PDF File Details

Part number:

PLL1000A

Manufacturer:

Z-Communications

File Size:

103.91kb

Download:

📄 Datasheet

Description:

Phase locked loop. NOTES: Reference Oscillator Signal: 5 MHz

PLL1000A Application

• Applications
• Basestations
• Mobile Radios
• Satellite Communications PERFORMANCE SPECIFICATIONS Frequency Range RMS Phase

TAGS

PLL1000A

Z-Communications

📁 Related Datasheet

PLL102-03 - Low Skew Output Buffer (PhaseLink Corporation)
PLL102-03 Low Skew Output Buffer FEATURES Frequency range 75 ~ 180MHz. Internal phase locked loop will allow spread spectrum modulation on reference c.

PLL102-04 - Low Skew Output Buffer (PhaseLink Corporation)
PLL102-04 Low Skew Output Buffer FEATURES Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference c.

PLL102-05 - Low Skew Output Buffer (PhaseLink Corporation)
PLL102-05 Low Skew Output Buffer FEATURES Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spectrum modulation on reference cl.

PLL102-10 - Low Skew Output Buffer (PhaseLink Corporation)
PLL102-10 Low Skew Output Buffer FEATURES Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference c.

PLL102-108 - Programmable DDR Zero Delay Clock Driver (PhaseLink Corporation)
PLL102-108 Programmable DDR Zero Delay Clock Driver FEATURES PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz. • D.

PLL102-109 - Programmable DDR Zero Delay Clock Driver (PhaseLink Corporation)
Preliminary PLL102-109 Programmable DDR Zero Delay Clock Driver FEATURES PLL clock distribution optimized for Double Data Rate SDRAM application up .

PLL102-15 - Low Skew Output Buffer (PhaseLink Corporation)
PLL102-15 Low Skew Output Buffer FEATURES Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spec trum modulation on reference c.

PLL103-01 - Low Skew Buffer (PhaseLink Corporation)
PLL103-01 Low Skew Buffers FEATURES Generate 18 copies of High-speed clock inputs. Supports up to four SDRAM DIMMS synchronous clocks. • Supports 2-wi.

PLL103-02 - DDR SDRAM Buffer (PhaseLink Corporation)
PLL103-02 DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS FEATURES • Generates 24 output buffers from one input. • Supports up to four DDR DIMMS. • .

PLL103-03 - DDR SDRAM Buffer (PhaseLink Corporation)
Preliminary PLL103-03 DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS FEATURES Generates 24-output buffers from one input. Supports up to 4 DDR DIM.