PLL102-05 Low Skew Output Buffer

PhaseLink Corporation

Description

PLL102-05 Low Skew Output Buffer .
The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC pa.

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Datasheet Specifications

Part number: PLL102-05
Manufacturer: PhaseLink Corporation
File Size: 255.92 KB
Datasheet: PLL102-05_PhaseLinkCorporation.pdf
Description: Low Skew Output Buffer

Features

* Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation).
* Zero input - output delay.
* Less than 700 ps device - device skew.
* Less than 250 ps skew between outputs.

Applications

* requiring zero output-output skew, all the outputs must equally loaded. www. DataSheet4U. com If the CLK(1-4) outputs are less loaded than CLKOUT, CLK(1-4) outputs will lead it; if the CLK(0-4) is more loaded than CLKOUT, CLK(1-4) will lag the CLKOUT. Since the CLKOUT and the CLK(1-4) outputs are ide

PLL102-05 Distributors

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PLL102-05 Low Skew Output Buffer PhaseLink Corporation

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