PLL102-04 - Low Skew Output Buffer

PhaseLink Corporation

PLL102-04 Datasheet Preview — Preview of PLL102-04 PDF

Datasheet Details

Part number	PLL102-04
Manufacturer	PhaseLink Corporation
File Size	269.36 KB
Description	Low Skew Output Buffer
Datasheet	PLL102-04_PhaseLinkCorporation.pdf

PLL102-04 Product details

Description

The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package.

Features

Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation).
Zero input - output delay.
Less than 700 ps device - device skew.
Less than 250 ps skew between outputs. www. DataSheet4U. com.
Less than 200 ps cycle - cycle jitter.
Output Enable function tri-state outputs.
3.3V operation.
Available in 8-Pin 150mil SOIC.

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Other Datasheets by PhaseLink Corporation

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PLL102-05 - Low Skew Output Buffer
PLL102-10 - Low Skew Output Buffer
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Published: Oct 28, 2008 |