Part number:
PLL102-04
Manufacturer:
PhaseLink Corporation
File Size:
269.36 KB
Description:
Low skew output buffer.
PLL102-04 Datasheet (269.36 KB)
* Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation).
* Zero input - output delay.
* Less than 700 ps device - device skew.
* Less than 250 ps skew between outputs
PLL102-04 Datasheet (269.36 KB)
PLL102-04
PhaseLink Corporation
269.36 KB
Low skew output buffer.
📁 Related Datasheet
PLL102-03 Low Skew Output Buffer (PhaseLink Corporation)
PLL102-05 Low Skew Output Buffer (PhaseLink Corporation)
PLL102-10 Low Skew Output Buffer (PhaseLink Corporation)
PLL102-108 Programmable DDR Zero Delay Clock Driver (PhaseLink Corporation)
PLL102-109 Programmable DDR Zero Delay Clock Driver (PhaseLink Corporation)
PLL102-15 Low Skew Output Buffer (PhaseLink Corporation)
PLL1000A PHASE LOCKED LOOP (Z-Communications)
PLL103-01 Low Skew Buffer (PhaseLink Corporation)
PLL103-02 DDR SDRAM Buffer (PhaseLink Corporation)
PLL103-03 DDR SDRAM Buffer (PhaseLink Corporation)
