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PLL102-04 Datasheet - PhaseLink Corporation

PLL102-04_PhaseLinkCorporation.pdf

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Datasheet Details

Part number:

PLL102-04

Manufacturer:

PhaseLink Corporation

File Size:

269.36 KB

Description:

Low skew output buffer.

PLL102-04, Low Skew Output Buffer

The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package.

It has four outputs that are synchronized with the input.

The synchronization is established via CLKOUT feed back to the input of the PLL.

Sinc

PLL102-04 Features

* Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation).

* Zero input - output delay.

* Less than 700 ps device - device skew.

* Less than 250 ps skew between outputs

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