74HC107 - Dual JK flip-flop
The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no.
7A.
74HC/HCT107 The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, clock (nCP) and re
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT107 Dual JK flip-flop with reset; negative-edge trigger Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge tr
