PCS3P623Z05A Datasheet - PulseCore Semiconductor

PCS3P623Z05A Timing-Safe Peak EMI reduction IC

PCS3P623Z05/09 is a versatile, 3.3V Zero-delay buffer memory interface systems. General Block Diagram PLL CLKIN DLY_CTRL CLKOUT1 CLKOUT2 CLKOUT3 PLL CLKIN MUX DLY_CTRL CLKOUTA1 CLKOUTA2 CLKOUTA3 CLKOUTA4 PCS3P623Z05A/B CLKOUT4 S2 S1 Select Input Decoding CLKOUTB1 CLKOUTB2 CLKOUTB3 PCS3P62.

PCS3P623Z05A Features

* Clock distribution with Timing-Safe™ Peak EMI Reduction Input frequency range: 20MHz - 50MHz Multiple low skew Timing-safe™ Outputs: PCS3P623Z05: 5 Outputs PCS3P623Z09: 9 Outputs

* External Input-Output Delay Control option Supply V

PCS3P623Z05A Datasheet (580.80 KB)