Description
February 2007 Cover Page HYS72T64[4/5]00HFD *3S *B HYS72T128[4/5]20HFD *3S *B HYS72T256[4/5]20HFD *3S *B ww.
using an Industry Standard High-Speed Differential Point-toPoint Link Interface at 1.
Features
* Detects errors on the channel and reports them to the host memory controller.
* Automatic DDR2 DRAM Bus Calibration.
* Automatic Channel Calibration.
* Full Host Control of the DDR2 DRAMs.
* Over-Temperature Detection and Alert.
* Hot Add-on and Hot
Applications
* Module organisation one rank 64M × 72, one rank 128M × 72, two ranks 128M × 72, two ranks 256M ×72
* JEDEC Standard Double Data Rate 2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8 V (± 0.1 V) power supply.
* Built with 512Mb DDR2 SDRAMs in 60-ball FBGA Chipsize Packages.
