HYB18T1G800BC Datasheet - Qimonda

HYB18T1G800BC 1-Gbit Double-Data-Rate-Two SDRAM

Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion. A 17-bit address bus for ×4 and ×8 organised components and a 16 bit address bus for ×16 components.

May 2007 www.DataSheet4U.com HY[B/I]18T1G400B[F/C](L) HY[B/I]18T1G800B[F/C](L) HY[B/I]18T1G160B[F/C](L) 1-Gbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.2 Internet Data Sheet www.DataSheet4U.com HY[B/I]18T1G[40/80/16]0B[C/F](L) 1-Gbit Double-Data-Rate-Two SDRAM HY[B/I]18T1G400B[F/C](L), HY[B/I]18T1G160B[F/C](L), HY[B/I]18T1G800B[F/C](L) Revision History: 2007-05, Rev. 1.2 Page All Subjects (major changes since last revision) Adapted internet .

HYB18T1G800BC Features

* The 1-Gbit Double-data-Rate SDRAM offers the following key features:

* Off-Chip-Driver impedance adjustment (OCD) and On

* 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O Die-Termination (ODT) for better signal quality

* DRAM organizations with 4, 8 and 16 d

HYB18T1G800BC Datasheet (3.86 MB)