HYI25D512160C Datasheet - Qimonda

HYI25D512160C 512-Mbit Double-Data-Rate SDRAM

Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bit.

November 2006 HYI25D512160C[C/E/F/T] www.DataSheet4U.com 5 1 2 - M b i t D o u b l e - D a t a - R a t e SD R A M DDR SDRAM Internet Data Sheet Rev. 1.0 Internet Data Sheet HYI25D512160C[C/E/F/T] 512-Mbit Double-Data-Rate SDRAM HYI25D512160C[C/E/F/T] Revision History: 2006-11, Rev. 1.0 Page www.DataSheet4U.com Subjects (major changes since last revision) Adapted internet edition Qimonda update, first final revision All All We Listen to Your Comments Any information within this document .

HYI25D512160C Features

* Double data rate architecture: two data transfers per clock cycle Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver DQS is edge-aligned with data for reads and is center-aligned with data for writes Differential clock inputs (CK and

HYI25D512160C Datasheet (1.85 MB)