* Double data rate architecture: two data transfers per clock cycle Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver DQS is edge-aligned with data for reads and is center-aligned with data for writes Differential clock inputs (CK and
HYI25D512160C Datasheet (1.85 MB)
HYI25D512160C
Qimonda
1.85 MB
512-mbit double-data-rate sdram.
November 2006
HYI25D512160C[C/E/F/T]
www.DataSheet4U.com
5 1 2 - M b i t D o u b l e - D a t a - R a t e SD R A M DDR SDRAM
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