HM63021 Datasheet - Renesas Technology

HM63021 2048-word x 8-bit Line Memory

Pin No. 1 2 3 4 to 11 12 13 www.DataSheet4U.com HM63021 Series Functions Mode input 1 (all modes) Read clock input (TBCE, DSC, TBC) Clock input (1H/2H, D) Read reset input (TBCE, DSC, TBC) Reset input (1H/2H, D) Data inputs (all modes) Write enable input (all modes) High impedance (TBCE, DSC) Write.

HM63021 Series 2048-word × 8-bit Line Memory The HM63021 is a 2048-word × 8-bit static serial access memory (SAM) with separate data inputs and outputs. Since it has an internal address counter, no external address signal is required and internal addresses are scanned serially. Using five different address scan modes, it is applicable to FIFO memories, double-speed conversions, 1H delay lines, and 1H/2H delay lines for digital TV signals. Its minimum cycle times are 28 ns and 34 ns, corwww.DataS.

HM63021 Features

* Five modes for various applications

* Corresponds to digital TV system with 4 fsc sampling (PAL, NTSC)

* Decoder signal output pin (fewer external circuits)

* Asynchronous read/write operation

* Separate address counters for read/write

* No address i

HM63021 Datasheet (142.95 KB)