9DB1233 Datasheet - Renesas

12-Output Differential Buffer

9DB1233 Features

* ▪ Twelve 0.7V current mode differential HSCL output pairs Features ▪ 3 selectable SMBus addresses; multiple devices can share the same SMBus segment ▪ 12 OE# pins; hardware control of each output ▪ PLL or bypass mode; PLL can dejitter incoming clock ▪ Selectable PLL bandwidth; minimizes jitter peak

9DB1233 General Description

The 9DB1233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB1233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selecta.

9DB1233 Datasheet (490.18 KB)