HD74SSTV16857 Datasheet - Renesas

1:1 14-bit SSTL_2 Registered Buffer

HD74SSTV16857 Features

* Supports LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input

* Differential SSTL_2 (Stub series terminated logic) CLK signal

* Flow through architecture optimizes PCB layout

* Ordering Information Part Name Package Type Package Code (Previous

HD74SSTV16857 General Description

The HD74SSTV16857 is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input. Data flow from D to Q is controlled by differential clock pins (CLK, CLK) and the RESET. Data is triggered on the positive edge of the posi.

HD74SSTV16857 Datasheet (245.03 KB)