HD74AC112 - Dual JK Negative Edge-Triggered Flip-Flop

Renesas

Datasheet Details

Part number	HD74AC112
Manufacturer	Renesas
File Size	209.33 KB
Description	Dual JK Negative Edge-Triggered Flip-Flop
Datasheet	HD74AC112-Renesas.pdf

The HD74AC112/HD74ACT112

individual J, K, Clock and asynchronous Set and Clear inputs to each flipflop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will perform according to the Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs on the falling edge of the clock pulse. Features.
Outputs Source/Sink 24 mA.
HD74ACT112 has TTL-Comp.

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Published: Dec 4, 2017 |