Datasheet4U Logo Datasheet4U.com

ICS91305I - High Performance Communication Buffer

Description

The ICS91305I is a high performance, low skew, low jitter clock driver.

It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal.

Features

  • Zero input - output delay.
  • Frequency range 10 - 133 MHz (3.3V).
  • 5V tolerant input REF.
  • High loop filter bandwidth ideal for Spread Spectrum.

📥 Download Datasheet

Datasheet preview – ICS91305I

Datasheet Details

Part number ICS91305I
Manufacturer Renesas
File Size 329.94 KB
Description High Performance Communication Buffer
Datasheet download datasheet ICS91305I Datasheet
Additional preview pages of the ICS91305I datasheet.

📁 Similar Datasheet

  • ICS91305I - High Performance Communication Buffer (Integrated Circuit Systems)
  • ICS91305 - High Performance Communication Buffer (Integrated Circuit Systems)
  • ICS91309 - High performance Communication Buffer (Integrated Circuit Systems)
  • ICS9131 - 32 KhZ Motherboard Frequency Generator (Integrated Circuit Systems)
  • ICS9133X - 32 kHz Motherboard Frequency Generator (Integrated Circuit Systems)
  • ICS9134-06 - (ICS9134-06 / ICS9134-07) 32 kHz Motherboard Frequency Generator (Integrated Circuit Systems)
  • ICS9134-07 - (ICS9134-06 / ICS9134-07) 32 kHz Motherboard Frequency Generator (Integrated Circuit Systems)
  • ICS9111-01 - 300Mhz Clock Generator (Integrated Circuit Systems)
  • ICS9111-03 - (ICS9111-03/04) Frequency Generator (Integrated Circuit Systems)
  • ICS9111-04 - (ICS9111-03/04) Frequency Generator (Integrated Circuit Systems)
Other Datasheets by Renesas

Full PDF Text Transcription

Click to expand full text
HIGH PERFORMANCE COMMUNICATION BUFFER DATASHEET ICS91305I Description The ICS91305I is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at speeds from 10 to 133 MHz. ICS91305I is a zero delay buffer that provides synchronization between the input and output. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than +/- 350 pS, the part acts as a zero delay buffer. The ICS91305I comes in an eight pin 150 mil SOIC package. It has five output clocks.
Published: |