ICS9112A-16 Datasheet PDF (Low Skew Output Buffer)

ICS9112A-16 - Low Skew Output Buffer

Description

The ICS9112A-16 is a high performance, low skew, low jitter clock driver.

It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal.

It is designed to distribute high speed clocks in PC systems operating at speeds from 25 to 133 MHz.

Features

Zero input - output delay.
Frequency range 25 - 133 MHz (3.3V).
High loop filter bandwidth ideal for Spread Spectrum.

Datasheet Details

Part number	ICS9112A-16
Manufacturer	Renesas
File Size	262.96 KB
Description	Low Skew Output Buffer
Datasheet	ICS9112A-16 Datasheet
Additional preview pages of the ICS9112A-16 datasheet.

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Full PDF Text Transcription

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ICS9112A-16 TM Low Skew Output Buffer General Description The ICS9112A-16 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in PC systems operating at speeds from 25 to 133 MHz. ICS9112A-16 is a zero delay buffer that provides synchronization between the input and output. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than +/- 350 pS, the part acts as a zero delay buffer. The ICS9112A-16 comes in an eight pin 150 mil SOIC or 173 mil TSSOP package. It has five output clocks.

Published: Jan 10, 2024 |