ICS9112-17 Datasheet - Integrated Circuit Systems

ICS9112-17 Low Skew Output Buffer

General a The ICS9112-17 is a high performance, low skew, low jitter .D buffer. zero delay It uses a phase lock loop (PLL) w technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute w speed high clocks in PC systems operating at speeds wfro.

ICS9112-17 Features

* Zero input - output delay Frequency range 25 - 133 MHz (3.3V) High loop filter bandwidth ideal for Spread Spectrum applications. Less than 200 ps cycle to cycle Jitter Skew controlled outputs Skew less than 250 ps between outputs

ICS9112-17_IntegratedCircuitSystems.pdf