ISL6412 Datasheet (Renesas) - Low-Noise LDO Regulator

ISL6412, Low-Noise LDO Regulator

DATASHEET ISL6412 Triple Output, Low-Noise LDO Regulator with Integrated Reset Circuit FN9067 Rev 1.00 Mar 20, 2007 The ISL6412 is an ultra low noise triple output LDO regulator with microprocessor reset circuit and is optimized for powering wireless chip sets.

The IC accepts an input voltage range of 3.0V to 3.6V and provides three regulated output voltages: 1.8V (LDO1), 2.8V (LDO2), and another ultra-clean 2.8V (LDO3).

On chip logic provides sequencing between LDO1 and LDO2 for the BBP/MAC

ISL6412 Features

* ultra low noise that does not typically exceed 30µV RMS to aid VCO stability. High integration and the thin Quad Flat No-lead (QFN) package makes the ISL6412 an ideal choice to power many of today’s small form factor industry standard wireless cards such as PCMCIA, mini-PCI and Cardbus-32. The ISL64