* Ultra-low power consumption technology
* VDD = single power supply voltage of 1.6 to 5.5 V
* HALT mode
* STOP mode
* SNOOZE mode RL78 CPU core
* CISC architecture with 3-stage pipeline
* Minimum instruction execution time: Can be changed from high speed (0.03125 μs: @ 32 MHz
R5F100PJAFB Datasheet (3.32 MB)
R5F100PJAFB
3.32 MB
16-bit single-chip microcontrollers.
Datasheet RL78/G13 RENESAS MCU R01DS0131EJ0350 Rev.3.50 Jun 30, 2020 True low-power platform (66 μA/MHz, and 0.57 μA for operation with only RTC an.
📁 Related Datasheet
R5F100PJAFA 16-Bit Single-Chip Microcontrollers (Renesas)
R5F100PFAFA 16-Bit Single-Chip Microcontrollers (Renesas)
R5F100PFAFB 16-Bit Single-Chip Microcontrollers (Renesas)
R5F100PGAFA 16-Bit Single-Chip Microcontrollers (Renesas)
R5F100PGAFB 16-Bit Single-Chip Microcontrollers (Renesas)
R5F100PHAFA 16-Bit Single-Chip Microcontrollers (Renesas)
R5F100PHAFB 16-Bit Single-Chip Microcontrollers (Renesas)
R5F100PKAFA 16-Bit Single-Chip Microcontrollers (Renesas)
R5F100PKAFB 16-Bit Single-Chip Microcontrollers (Renesas)
R5F100PLAFA 16-Bit Single-Chip Microcontrollers (Renesas)
