R5F11CCC Description
RL78/I1E RENESAS MCU 1.OUTLINE 1.1 .R5F11CCC Features
* Ultra-low power consumption technology VDD= 2.4 to 5.5 V HALT mode STOP mode SNOOZE mode RL78 CPU core CISC architecture with 3-stage pipeline Minimum instruction execution time: Can be changed from high speed (0.03125 s: @ 32 MHz operation with high-speed on-chip oscillator or PLL clock)Note to uR5F11CCC Applications
* (M; TA = 40 to +125C): 0.04167 s @ 24 MHz operation with high-speed on-chip oscillator or PLL clock Code flash memory Code flash memory: 32 KB Block size: 1 KB Prohibition of block erase and rewriting (security function) On-chip debug function Self-programming (with boot swap function/flash shie
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