R5F5110JADLF, R5F51105AGFM - 32 MHz 32-bit RX MCUs

Renesas

The R5F5110JADLF by Renesas is a 32 MHz 32-bit RX MCUs. Below is the official datasheet preview.

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R5F5110JADLF 32 MHz 32-bit RX MCUs by Renesas - Datasheet Preview — Official preview page of the **R5F5110JADLF** 32 MHz 32-bit RX MCUs datasheet (Renesas).

Datasheet Details

Part number	R5F5110JADLF, R5F51105AGFM
Manufacturer	Renesas
File Size	0.96 MB
Description	32 MHz 32-bit RX MCUs
Datasheet	R5F51105AGFM-Renesas.pdf
Note	This datasheet PDF includes multiple part numbers: R5F5110JADLF, R5F51105AGFM. Please refer to the document for exact specifications by model.
Additional preview pages of the R5F5110JADLF datasheet.

R5F5110JADLF Product details

Description

CPU CPU Maximum operating frequency: 32 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per one clock cycle Address space: 4-Gbyte linear Register set General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One 64-bit register Basic instructions: 73 DSP instructions: 9 Addressing modes: 10 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian

Features

32-bit RX CPU core.
32 MHz maximum operating frequency Capable of 50 DMIPS when operating at 32 MHz.
Accumulator handles 64-bit results (for a single instruction) from 32-bit × 32-bit operations.
Multiplication and division unit handles 32-bit × 32-bit operations (multiplication instructions take one CPU clock cycle).
Fast interrupt.
CISC Harvard architecture with five-stage pipeline.
Variable-length instruction format, ultra-compact code.
On-chip debuggi.

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Published: Jan 1, 2016 |