R5F52108ADFP - 50-MHz 32-bit RX MCUs

Renesas

R5F52108ADFP Datasheet Preview — Preview of R5F52108ADFP PDF

Datasheet Details

Part number	R5F52108ADFP
Manufacturer	Renesas ↗
File Size	938.47 KB
Description	50-MHz 32-bit RX MCUs
Datasheet	R5F52108ADFP_Renesas.pdf

R5F52108ADFP Product details

Description

Maximum operating frequency: 50 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register set of the CPU General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One 64-bit register Basic instructions: 73 DSP instructions: 9 Addressing modes: 10 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-b

Features

32-bit RX CPU core.
Max. operating frequency: 50 MHz Capable of 78 DMIPS in operation at 50 MHz.
Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations.
Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle).
Fast interrupt.
CISC Harvard architecture with 5-stage pipeline.
Variable-length instructions, ultra-compact code.
On-chip debugging circuit.
Lo.

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Published: Jun 3, 2012 |