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R5F521A7BDLJ Datasheet - Renesas

R5F521A7BDLJ MCUs

CPU CPU * Maximum operating frequency: 50 MHz * 32-bit RX CPU * Minimum instruction execution time: One instruction per state (cycle of the system clock) * Address space: 4-Gbyte linear * Register set General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Ac.

R5F521A7BDLJ Features

* 32-bit RX CPU core

* Max. operating frequency: 50 MHz Capable of 78 DMIPS in operation at 50 MHz

* Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations

* Multiplication and division unit handles 32- × 32-bit operations (multiplication instructi

R5F521A7BDLJ Datasheet (1.78 MB)