R5F521A8BDFP - MCUs

Product Overview

Renesas

Datasheet Details

Part number	R5F521A8BDFP
Manufacturer	Renesas
File Size	1.78 MB
Description	MCUs
Datasheet	R5F521A8BDFP Datasheet
Additional preview pages of the R5F521A8BDFP datasheet.

Product details

Description

CPU CPU Maximum operating frequency: 50 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register set General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One 64-bit register Basic instructions: 73 DSP instructions: 9 Addressing modes: 10 Data arrangement Instructions: Little endian Data: Selectable as little endian or

Features

32-bit RX CPU core.
Max. operating frequency: 50 MHz Capable of 78 DMIPS in operation at 50 MHz.
Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations.
Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle).
Fast interrupt.
CISC Harvard architecture with 5-stage pipeline.
Variable-length instructions, ultra-compact code.
Memory protection unit.
On-ch.

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Published: Apr 28, 2016 |