R5F523T5ADFL Datasheet (Renesas)

R5F523T5ADFL, MCU

CPU CPU * Maximum operating frequency: 40 MHz * 32-bit RX CPU (RX v2) * Minimum instruction execution time: One instruction per clock cycle * Address space: 4-Gbyte linear * Register set General purpose: Sixteen 32-bit registers Control: Ten 32-bit registers Accumulator: Two 7

R5F523T5ADFL Features

* 32-bit RX CPU core

* Max. operating frequency: 40 MHz Capable of 65.6 DMIPS in operation at 40 MHz

* Enhanced DSP: 32-bit multiply-accumulate and 16-bit multiply-subtract instructions supported

* Built-in FPU: 32-bit single-precision floating point (compliant to IEEE754)

* Divi