RT9173C Datasheet - Richtek Technology Corporation

RT9173C 2A Sink/Source Bus Termination Regulator

VIN (Pin 1) Input voltage which supplie s current to the output pin. Connect this pin to a well-decoupled supply voltage. To prevent the input rail from dropping during large load transient, a large, low ESR capacitor is recommended to use. The capacitor should be placed as close as possible to the .

RT9173C Cost-Effective, 2A Sink/Source Bus Termination Regulator General D escription The RT9173C is a si mple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 a nd SSTL_18 or other spe cific interfaces such a s HSTL, SCSI-2 a nd SCSI-3 etc. device s requirements. The regulator is ca pable of a ctively sinking or sourcing up to 2Awhile regulating a n output voltage to within 40mV . The.

RT9173C Features

* include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down prote ction. The RT9173C are available in the SOP-8 (Exposed Pad) surface mount pa ckages. Features z z z z z z z z z z z z z Ideal for DDR-I, DDR-II and DDR-I

RT9173C Datasheet (373.81 KB)