M48Z128V - 5.0V OR 3.3V / 1 Mbit (128 Kbit x 8) ZEROPOWER SRAM
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3 Logic Diagram (Figure 2.) .
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3 Signal Names (Table
M48Z128V Features
* SUMMARY s INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY s Figure 1. 32-pin PMDIP Module CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS OF DATA RETENTION IN THE ABSENCE OF POWER BATTERY INTERNALLY ISOLATED UNTIL POWER IS FIRST APPLIED AUTOMATIC POWER-FAIL C
