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M74HC112 Datasheet - ST Microelectronics

M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

M54HC112 M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR . . . . . . . . HIGH SPEED fMAX = 67 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS112 B1R (Plastic Package) F1R (Ceramic Package) M1R .

M74HC112 Features

* individual J,K, clock, and asynchronous set and clearinputs for each flip-flop. When the clock goes high, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is high and the bistable will function as shown in the truth

M74HC112 Datasheet (251.26 KB)

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Datasheet Details

Part number:

M74HC112

Manufacturer:

STMicroelectronics ↗

File Size:

251.26 KB

Description:

Dual j-k flip flop with preset and clear.

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M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR ST Microelectronics

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