* both true (Y) and complement (W) outputs as well as STROBE input. The STROBE must be a low logic level to enable this device. When the STROBE input is high, both outputs are in the high impedance state. When enabled, address information on the data select inputs determines which data input is routed
M74HC251 Datasheet (249.81 KB)
M74HC251
249.81 KB
8 bit sipo shift register.
M54HC251 M74HC251 8 BIT SIPO SHIFT REGISTER . . . . . . . . HIGH SPEED tPD = 14 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA.
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