M74HC251 - 8 BIT SIPO SHIFT REGISTER
M54HC251 M74HC251 8 BIT SIPO SHIFT REGISTER .
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HIGH SPEED tPD = 14 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C 6 V HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS251 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro
M74HC251 Features
* both true (Y) and complement (W) outputs as well as STROBE input. The STROBE must be a low logic level to enable this device. When the STROBE input is high, both outputs are in the high impedance state. When enabled, address information on the data select inputs determines which data input is routed
