M74HCT137 Datasheet - ST Microelectronics

M74HCT137 3 TO 8 LINE DECODER/LATCH INVERTING

The M54/74HCT137 is a high speed CMOS3TO8LINE DECODER/LATCH (INVERTING) fabricated in silicon 2 gateC MOStechnology. Ithas the samehigh speed performance ofLSTTL combined with trueCMOSlow power consumption. This device is a 3 to 8 line decoder with latches onthe three address inputs. When GLgoes fro.

M54HCT137 M74HCT137 3 TO 8 LINE DECODER/LATCH (INVERTING) . . . . . . . HIGH SPEED tPD = 17 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8V (MAX) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL PIN AND FUNCTION COMPATIBLE WITH 54/74LS137 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) DE.

M74HCT137 Datasheet (260.84 KB)