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M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

M74HC112 Description

M54HC112 M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR *...HIGH SPEED fMAX = 67 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 2.
The M54/74HC112 is a high speed CMOS DUAL J-K FLIP-FLOP WITH PRESET AND CLEAR fabricated in silicon gate C2MOS technology.

M74HC112 Features

* individual J,K, clock, and asynchronous set and clearinputs for each flip-flop. When the clock goes high, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is high and the bistable will function as shown in the truth

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DUAL J-K FLIP FLOP WITH PRESET AND CLEAR ST Microelectronics
ST Microelectronics M74HC112-like datasheet