K4T51043QB-ZCD5 Datasheet | Samsung Semiconductor

Feature 2. Package Pinout/Mechanical Dimension & Addressing 2.1 Package Pinout & Mechanical Dimension 2.2 Input/Output Function Description 2.3 Addressing 3. Absolute Maximum Rating 4. AC & DC Operating Conditions & Specifications Page 2 of 28 Rev. 1.5 July 2005 512Mb B-die DDR2 SDRAM 0. Ordering Information Organization 128Mx4 64Mx8 32Mx16 DDR2-533 4-4-4 K4T51043QB-GCD5 K4T51043QB-ZCD5 K4T51083QB-GCD5 K4T51083QB-ZCD5 K4T51163QB-GCD5 K4T51163QB-ZCD5 DDR2-400 3-3-3 K4T51043QB-GCCC K4T51043QB-ZCCC K4T51083QB-GCCC K4T51083QB-ZCCC K4T51163QB-GCCC K4T51163QB-ZCCC .. DDR2 SDRAM Package 60 FBGA 60 FBGA 60 FBGA 60 FBGA 84 FBGA 84 FBGA Note : Speed bin is in order of CL-t RCD-t RP. 1.Key Features Speed CAS Latency t RCD(min) t RP(min) t RC(min) DDR2-533 4-4-4 4 15 15 55 DDR2-400 3-3-3 3 15 15 55 Units t CK ns ns ns - JEDEC standard 1.8V ± 0.1V Power Supply - VDDQ = 1.8V ± 0.1V - 200 MHz f CK for 400Mb/sec/pin, 267MHz f CK for 533Mb/sec/ pin - 4 Banks - Posted CAS - Programmable CAS Latency: 3, 4, 5 - Programmable Additive Latency: 0, 1 , 2 , 3 and 4 - Write Latency(WL) = Read Latency(RL) -1 - Burst Length: 4 , 8(Interleave/nibble sequential) - Programmable Sequential / Interleave Burst Mode - Bi-directional Differential Data-Strobe (Single-ended datastrobe is an optional feature ) - Off-Chip Driver(OCD) Impedance Adjustment - On Die Termination - Special Function Support -High Temperature Self-Refresh rate enable - Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C - Package: 60ball FBGA - 128Mx4/64Mx8 , 84ball FBGA 32Mx16 - All of Lead-free products are pliant for Ro HS The 512Mb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 4 banks, 16Mbit x 8 I/Os x 4banks or 8Mbit x 16 I/Os x 4 banks device. This synchronous device achieves high...